The present invention relates to electrical circuits, specifically to an assembly for configuring electrical circuits.
Computer systems are increasingly using source synchronous bus designs, which have extremely narrow timing windows. To ensure the collection of correct data at a receiver, a driver must send a clocking signal that is centered as much as possible in a narrow timing window. Typically, the clocking signal arrives just after a data signal arrives at a receiver, and the clocking signal latches in the data into the receiver. The receiver needs a certain setup time to allow it to prepare to receive a data signal, and the receiver also has a hold time requirement which guarantees that the data signal is held at the receiver for a sufficient time to be sampled correctly. Thus, for the receiver to latch in valid data at the correct times, as dictated by the setup and hold times, the clocking signal must be closely centered in the timing window.
However, the operating frequencies of computer systems are always increasing, and timing problems can occur at the maximum and minimum operating frequencies of a given design. For example, at low frequencies setup time problems can occur, which means that the clocking signal arrives too quickly; at high frequencies hold time problems can occur, which means that the clocking signal arrives too slowly. In both situations, the clocking signal is not guaranteed to latch in the correct data.
A conventional solution to the timing problems is to compromise between the low and high frequencies such that one board can be used for a range of operating frequencies. However, this is not always possible or practical. Nonetheless, to achieve this compromise, the trace lengths of the clocking signal pathways and the data signal pathways must have some length differential among them.
In a source synchronous bus design, it is usually desirable to decrease trace length differences. Trace length differences can exacerbate setup problems at low frequencies and hold problems at high frequencies. A variable delay clock trace would help mitigate these timing problems by adjusting the clock delay for a given frequency. This would then allow a single board to be manufactured and used for applications at both low frequencies and high frequencies, thereby saving money by eliminating the need to manufacture multiple boards.
A variable delay path circuit that has at least two delay paths of different lengths is disclosed. In one embodiment, the circuit includes a central processing unit and a memory device that are connectable through either a first delay path or a second delay path.